1. Field of the Invention
The present invention relates to line scan photo sensors. In particular, the invention relates to a sensor architecture and method that increases the photo response by time delay and integration without compromising the sensor""s blue and UV response.
2. Description of Related Art
In a line scan sensor, an image conjugate is scanned across a linear array of sensor pixels and/or a linear array of sensor pixels are scanned across an image conjugate. To achieve a higher speed sensor under the same ambient light conditions, the sensor must have pixels with a higher response to the same ambient light. Known sensors increase the response to ambient light conditions using a TDI architecture (Time Delay and Integrate architecture). TDI sensors are typically formed in a rectangular format where the image conjugate to be sensed moves across the face of the sensor pixels at the exact same rate that the photo charge accumulating in the pixels is transferred along the direction of a vertical CCD register so that the end of the vertical CCD register includes the accumulated photo charge generated by a single image area but accumulated over an extended time.
The photo charge in a TDI CCD sensor is clocked along the CCD registers under the influence of electric fields caused by clock voltages applied to the CCD gate electrodes, typically formed of doped polycrystalline silicon (commonly referred to as poly). The doped polycrystalline silicon conducts electrical signals, and infrared light passes through the doped polycrystalline silicon with ease; however, blue light and/or ultraviolet light are absorbed in the polycrystalline silicon layers. Such typical TDI CCD sensors lack a good response to blue light and/or UV light.
To improve response to blue light and/or UV light, linear arrays of photodiodes, and/or pinned photodiodes (PPD) are commonly used. Photodiodes and PPD""s have good response to blue light and/or UV light at least in part because they are not covered by poly layers. Therefore, known TDI architectures are not useable.
In known sensors, the approach to improved response has been to try to increase the charge conversion efficiency (CCE) in a single linear array of photodiodes and/or PPD""s. The CCE is process dependent, and a very good (and expensive) process is required to achieve very high CCE. Increasing the CCE also reduces the full well capacity, resulting in higher photon shot noise at saturation. The architecture of the present invention provides a two times increase in the response to light and a 30% reduction in photon shot noise in the sensor.
It is an object to the present invention to provide a line scan sensor with increased response to light stimulation. It is a further object of the present invention to achieve the increased response without a loss of blue or UV response.
These and other objects are achieved in a line scan sensor that includes first and second rows of pixels, corresponding first and second readout registers, a plurality of first channel structures, and a plurality of second channel structures. Each channel structure of the first channel structures is disposed between a corresponding pixel of the first row of pixels and a corresponding register element of the first readout register. Each channel structure of the second channel structures is disposed between a corresponding pixel of the second row of pixels and a corresponding register element of the second readout register.
These and other objects are achieved in an alternative embodiment of a line scan sensor that includes first and second rows of pixels, corresponding first and second readout registers, and a first clocking structure disposed between the first row of pixels and the first readout register. The first clocking structure includes a transfer gate electrode and a delay well electrode.
These and other objects are achieved in another alternative embodiment of a line scan sensor that includes first and second rows of pixels, a delay register coupled to the first row of pixels, a first readout register coupled to the delay register, and a second readout register coupled to the second row of pixels.
These and other objects are achieved in a method that includes applying a transfer clock pulse to a transfer gate electrode of a first clocking structure and a transfer gate electrode of a second clocking structure, applying a first delay clock pulse to a delay well electrode of the first clocking structure after the transfer clock pulse is applied, and applying a second delay clock pulse to a delay well electrode of the second clocking structure before the transfer clock pulse is applied.
These and other objects are achieved in an alternative embodiment of a method that includes a first and a second step. The first step includes transferring photo charges in a delay register into a first readout register, transferring photo charges in a first storage register into the delay register, and transferring photo charges in a second storage register into the second readout register. The second step includes collecting photo charges in the first storage register, collecting photo charges in the second storage register, shifting photo charges in a first readout register toward a first output, and shifting photo charges in a second readout register toward a second output.
These and other objects are achieved in another alternative embodiment of a method that includes collecting a first line of photo charges from a first line array of pixels, delaying the first line of charges, collecting a second line of charges from a second line array of pixels, shifting the delayed first line of charges toward a first output while simultaneously shifting the second line of charges toward a second output, and combining the first and second outputs.